Hardware Architecture

ECG input stage · patient isolation · protection · power · board layout — based on the 2026-10-11 development-start edition (rev3), block-level summary

1. Starting point — confirmed specifications

This device touches the human body. Patient-contact isolation and leakage current were therefore taken as the starting point of the design. Development priorities are ① reliability and patient protection → ② new technology and advancement → ③ after-sales service, maintenance and future upgrades, in that order.

2. Overall block diagram

Green = patient island, yellow band = isolation barrier, purple = secondary side, orange = power. The orange dashed chip is the 12-lead option. The only parts crossing the barrier are the isolator (ISO7762) and isolated power (UCC12050) packages.

3. ECG input stage

Chip configuration — two AFE159RP8 Design default

U1 alone handles the basic 5 electrodes. U1 covers the I · II · III (direct) · V (= C − WCT) · calib channels plus pace detection, RLD drive and respiration (option). For the 12-lead option, U2 handles V1–V6, a separate calib, and a II channel for cross-checking between chips.

The reason for two chips is channel count. Doing 12-lead with one 8-channel chip fills it with I · II · V1–V6 alone, leaving no room for the confirmed-spec direct lead III measurement and calib.

12-lead option expansion method Design default

• The option circuitry (U2, the C1–C6 protection chains and relays) is mounted on the main board from the start and enabled by firmware activation and the option cover.
• This way, after-sales service does not require opening the patient island, and isolation and leakage testing can be done in one pass.
• The C1–C6 sockets sit under a hinged cover. Basic users see only 5 sockets, reducing misconnection.

V1 / V5 switch Confirmed (selection · display) · implementation Design default

• There is one measurement circuit. The chest electrode enters through the same path whether it is V1 or V5.
• The switch is a marker telling the device "where the chest electrode was placed." It is on the main-unit (secondary) side and the MCU reads it on two lines, so it does not cross the isolation.
• Changing it changes the on-screen label, shows placement guidance for that position, and logs an event. The waveform is not interrupted.
• On a contact fault (both lines in the same state), the label changes to "V?" and a technical alarm is raised.
• The device cannot determine where the electrode was actually placed. In 12-lead mode the switch is ignored and "12-lead" is displayed.

Connectors · shielding

• Electrode connectors are DIN 42802 touch-proof sockets: 5 basic + 6 under the option cover. Panel socket part number Unverified
• The simulator input jack has a different shape from the patient connectors to prevent misinsertion.
• DIN single-pole sockets have no shield contact, so instead of lead-wire shield drive, a board guard ring and an input-stage shield-can footprint are used. Design default

Lead-off · pace

• Lead-off uses the chip's built-in DC method continuously, with AC impedance measurement for periodic checks. The name of a detached electrode is shown on screen.
• Pace pulses use the chip's built-in detection and only the detection flag is read. The input stage's job is not to distort the pulse shape, so no differential capacitor is placed in the input network. Design default

4. Input protection

Every signal electrode has the same 3-stage protection chain. Per the confirmed spec, the pulse resistors are on the board, not in the lead wires.

• Defibrillation protection is included as the default Design default. It is not mandatory by standard for the home-use category, but the rationale is that patient protection is priority #1, and with the 12-lead option there are 10 electrodes, which a caregiver would struggle to remove quickly. If dropped, only the discharge tube positions are left empty on the same board.
• Single-fault criterion — the resistors are split into equal values so that if any one shorts, the leakage current stays within the allowed limit. The first draft exceeded this condition.
• High-voltage zone layout — resistors are placed right behind the sockets so that only the stretch from socket to first resistor is a high-voltage zone. This zone is copper-free on all layers, kept at least 8 mm from neighboring electrodes, and slotted. Guard and ground planes are not laid under this zone.
• Pitfall found — during calculation it was found that if a discharge tube stays in glow state, the chip supply could be pulled up, so one more clamp was added on the chip's analog supply. To be measured on the test bench.
• Whether the pulse resistor withstands a single defibrillation pulse has not been confirmed from datasheet charts Unverified. If insufficient, it will be split into three pieces.

5. Patient isolation

• Creepage and clearance 8 mm — a value set targeting 2 MOPP. The isolated power UCC12050 and the digital isolator ISO7762DW are both 2 MOPP certified parts. Design default
• There is no connector between the island and the secondary side. Only isolation component packages cross the barrier.
• ECG data is passed over isolated SPI. The raw pace signal is too large to stream continuously over isolated SPI, so only the chip's detection result is received.
• Relays inside the island are driven one at a time in sequence so that island power does not sag.
• The metal enclosure is not connected to island ground. Wireless antennas are placed as far as possible from the ECG sockets and input stage.
• Isolation-barrier leakage current exists only as a calculated value that omits board stray capacitance; it will be confirmed by measurement. Unverified

6. Power architecture

• Hot-swap — the two packs discharge together through ideal diodes, so removing one pack causes no power switchover moment.
• Outage switchover — the hardware (LTC1760) has already moved to battery first; software only changes the mode afterwards. In outage mode the display is dimmed and turned off at night, but measurement, recording and alarms continue. Design default
• Auto restart on AC return — after shutting down from battery depletion, the unit turns on without a button press when AC returns. Design default
• 2-stage interlock for measurement while charging — hardware logic turns on patient island power only "when AC is absent, or measurement while charging has been released." Stage 1 is a test-bench-only jumper; stage 2 is released on the board after passing measurement. It is a hardware interlock that SoM software cannot change.
• Preparing for LTC1760 discontinuation — production status was checked on an archived product page; current status is Unverified. As an alternative, a TI parts combination (LM5050-1 · BQ25731 · LM74502H) has been prepared. Its weakness is that charging must then be handled by host firmware.

Power protection — concept by stage

• Input: reverse polarity · overvoltage cutoff · surge absorption · input overcurrent limit
• Battery: power-path cutoff on load short, pack built-in protection, hardware overcharge ceiling, keying against reverse pack insertion, hot-swap ESD protection
• Rails: buck built-in current limit, panel power load switch, hard undervoltage cutoff
• Thermal: isolated-power thermal shutdown; by pack temperature, reduce in the order charging inhibit → brightness → CPU

Eliminating audible noise Confirmed (goal) · method Design default

• All switchers are synchronized at a fixed frequency divided from a single master clock. Burst/PFM modes that create audio-band components are not used; the bucks run in forced PWM.
• The 3.3 V buck in the earlier design had no forced PWM per its datasheet, so it was changed to LT8640S. Spread spectrum is turned off because its modulation frequency is in the audio band.
• The backlight controls brightness of its 5 LED strings by current only, without PWM (LP8866S).
• Inductors are metal-molded types, small capacitors are types without piezoelectric singing, and bulk capacitors are polymer.
• Unavoidable SpO2 LED pulse locations are handled with non-singing parts and judged by an audible noise test.

24-hour battery · fanless

• Fanless: SoM heat goes out through thermal pad → heat spreader → aluminum back plate. The charger is placed in a corner away from the pack bay and SoM; the pack bay is thermally isolated and placed in the lower part of the enclosure.
• Calculation showed that in the worst combination (maximum load + charging both packs + high ambient temperature), the enclosure internal temperature limit may be exceeded. Power management therefore does not allow that combination simultaneously (CPU cap while charging, charging inhibit by pack temperature). Figures will be confirmed by thermal equilibrium testing.
• Switcher inductors are placed in the board corner opposite the ECG input and electrode connectors.

7. Board layout

8. Design history

After the first hardware design on 2026-09-24, the main parts changed with the 2026-10-11 specification upgrade decision.

9. Remaining unverified items · next measurements

• AFE159RP8 detailed datasheet — 14 items including pinout, absolute maximum ratings, lead-off current, pace range, multi-chip sync and power sequencing. Circuitry around the chip will be drawn after receiving the material. Production status was confirmed as Active on the product page and appendix. Unverified
• Differences from an alternative chip combination (ADI ADAS1000 + ADAS1000-2) have been compared. Since the spec is AFE159RP8, the chip will not be changed.
• Current production status of LTC1760, battery pack contact and communication conditions, some passive component datasheets Unverified
• Light-load noise of the SoM internal power chips and the adapter Unverified
• Next measurements: simulated end-of-life pack 24 hours · audible noise · island current · backlight luminance · interlock truth table · auto restart on AC return · isolation leakage · thermal equilibrium